1. Field of the Invention
This invention relates to vias, and more particularly to use of a via interconnect that interlocks with a conductive layer to prevent delamination.
2. Background of the Invention
As the size of semiconductor devices decrease, the density of semiconductor devices increases, and the interconnect density within substrates and printed circuit board (“PCB”) increases. To provide such increased interconnections, the interconnect dimensions and spacing decrease, and the number of interconnect layers increase. Multiple interconnect layers may be fabricated so that conductive layers are separated by dielectric layers. A via in a semiconductor substrate or PCB provides an electrical connection between conductors on different layers of the substrate or PCB. For example, a via may provide an electrical connection from the surface of the substrate or PCB to a conductive trace within the substrate or PCB.
FIG. 1 is a side cross section view of a via 102 that electrically connects a top conductor 110 (plane or trace) with a bottom conductor 106 (plane or trace). The top conductor 110 is separated from the bottom conductor 106 by a dielectric layer 104. The via 102 is meant to extend through the dielectric layer 104 from the top conductor 110 to make contact with the top of the bottom conductor 106 to connect the top conductor 110 with the bottom conductor 106. However, thermal expansion of the dielectric layer 104 can produce a vertical tensile stress on the via 102. This stress can cause the bottom of the via 102 to detach from the bottom conductor 106, creating a delamination void 108. This delamination void 108 means that the via 102 does not correctly electrically connect the conductor 110 to the bottom conductor 106. Semiconductor substrates and PCBs with such delamination voids 108 likely will not work correctly.